1. Field of the Invention
The present invention relates to an encoding apparatus.
2. Description of the Related Art
In recent years, the use of DVD (Digital Versatile Disk) media of a write-once type, a rewritable type, and the like has been widespread. For the purpose of improving quality of record and playback, the method of recording on a DVD medium is standardized so as to record data produced by performing a scrambling process, an ECC (Error Correcting Code) encoding process, and an 8-to-16 modulation process on data to be recorded (record data). Hereinafter, the series of these processes performed on record data is called an “encoding process”, and an apparatus that performs this encoding process is called an “encoding apparatus”.
The encoding process for DVDs will be described based on FIGS. 11, 12, 13, and 14.
FIG. 11 is a conceptual view for explaining the data sector of a DVD.
First, record data is divided into data pieces of 2,048 bytes. The data pieces are each called main data, and a header of 12 bytes is added to the head of the main data. This header comprises an ID (Identification Code) of 4 bytes, an ID error detection code (IED) of 2 bytes, and a reserved field of 6 bytes for, e.g., copy protect information (CPM: Copyright Management Code). An EDC (Error Detection Code) of 4 bytes is appended to the main data. This EDC is an error detection code for the main data having the header added thereto.
A total of 2,064 bytes of data having the header and EDC added thereto is handled as a data sector of 172 bytes (columns) by 12 rows with 172 bytes as a unit. Note that a scrambling process using PN (Pseudo-random Noise) sequence addition is performed on the 2,048 byte main data of the data sector by using information indicated by bits 7 through 4 of the ID included in the header as a scramble key.
FIG. 12 is a conceptual view for explaining one ECC block of a DVD.
Sixteen data sectors together form a matrix of 172 bytes by 192 rows (hereinafter, called a data sector group). Inner parities PI (Inner Code Parities) that are each an error correction code for the 172 byte data group of a row, and outer parities PO (Outer Code Parities) that are each an error correction code for the 192 byte data group of a column are generated and appended to this data sector group. Note that the inner parities PI and outer parities PO are generated by performing predetermined processes on the scrambled main data of 2,064 bytes.
The Data having the outer parities PO and inner parities PI appended thereto, which is of 182 bytes (columns) by 208 rows, is called one ECC block, and handled as a unit to perform error correction and error detection and the like. Furthermore, the rows of the one ECC block are rearranged as shown in FIG. 13, wherein the sixteen rows of the outer parities PO are separately disposed at the back of the respective data sectors, to each row of which an inner parity PI is appended. Here, data of 182 bytes by 13 rows wherein inner parities PI of 10 bytes and a row of the outer parities PO are appended to one data sector is handled as a record sector. After the 8-to-16 modulation and NRZI conversion are performed on data of one ECC block made up of 16 record sectors, the data is recorded on a DVD medium.
FIG. 14 is a view of the configuration of a system comprising an encoding apparatus that performs the above encoding process.
An encoding apparatus 810 temporarily writes record data transferred from a host computer 800 into a DRAM (Dynamic Random Access Memory) 820. DRAM 820 is a volatile memory suitable for higher integration such as an SDRAM (Synchronous DRAM), and is usually used as buffer memory for a large amount of record data that a DVD medium handles.
Encoding apparatus 810 performs on record data stored in DRAM 820 the encoding process, i.e., a series of header generation and addition, scrambling, EDC generation and addition, and generation and addition of outer parities PO and inner parities PI, one by one sequentially. See for example Japanese Patent Application Laid-open Publication No. 2004-22130.
Because the scrambling, EDC generation and addition, and generation and addition of outer parities PO and inner parities PI of the encoding process series are sequentially performed in encoding apparatus 810 as shown in FIG. 14, a wait time (process-start wait time) occurs for which another process subsequent to each process of the encoding process series has to wait to start until the process finishes.
Moreover, each process of the encoding process entails access (write/read) to a memory device such as DRAM 820. Hence, by performing sequentially the processes of the encoding process, times (access times) required for access to the memory device such as DRAM 820 involved in the processes accumulate.
As described above, with the conventional scheme for the encoding process, it is difficult to further speed the encoding process because of the process-start wait time and accumulation of memory access times mentioned above.